PAWEŁ - ELECTRONICS ENGINEER

Digital & Hardware design · Signal & Data processing
Location: Warsaw, Poland
Email: mamior12(at)gmail.com

About

I am an FPGA engineer focused on turning algorithms into efficient hardware. I enjoy working with software and hardware combining two worlds together.

My experience spans from early architecture exploration and hardware/software partitioning, through RTL design and verification, to synthesis, timing analysis, and on‑board bring‑up. I care about readability, testability, and repeatable builds.

Core skills

FPGA & Digital design
  • RTL design in HLS, VHDL, and SystemVerilog testbenches.
  • Pipelining, resource sharing, and area/speed trade-offs.
  • Implementation on AMD/Xilinx devices: FPGA, SoC, Alveo, MPSoC & RFSoC.
VHDL SYSTEMVERILOG Vitis HLS AMD/XILINX
Hardware design
  • PCB design including digital and analog data paths
  • Project suitable for complete production with documentation.
  • Firmware and software for communication with the board.
Altium Designer LtSpice STM32 PCB
Signal and data processing
  • Post-processing recorded signals in Matlab, Octave, and python modules.
  • Real-time processing of signals on FPGA/uControllers.
  • Data acquisition, recording signals for further processing.
Matlab Octave Python
Tools & flows
  • Vivado, Quartus, and vendor IP integration.
  • Version control and automated builds (Git, CI).
  • Python scripts for generation, verification and helpful tools.
VIVADO GIT CI PYTHON
Interfaces & domains
  • AXI, AHB, and simple streaming buses.
  • High‑speed data paths and buffering.
  • SoC integration and HW/SW co‑design.
  • PCI-Express: DMA from FPGA to CPU memory
AXI STREAMING SOC PCI-E

Selected FPGA‑related projects

Streaming signal processing pipeline
Goal Real‑time processing chain for incoming data stream with strict latency constraints.
Role Architecture, RTL implementation, and timing closure.
Highlights Introduced pipeline stages and coefficient sharing, reduced critical path, and achieved timing at target frequency with margin.
Custom AXI‑based peripheral
Goal Design a configurable accelerator as an AXI‑Lite/AXI‑Stream peripheral for an SoC.
Role Bus interface design, RTL coding, testbench, and integration with software driver.
Highlights Clean separation of control/status, datapath, and interface logic; self‑checking testbench with protocol assertions.
Small soft‑core & peripheral playground

Hobby project used to try out new ideas, bus interconnects, and verification strategies. The repository contains multiple small IP blocks, each with focused testbenches and documentation.

Selected hardware-related projects

FMC add-on
Goal Add-on board with FMC connector to expand evaluation board with custom hardware.
Role Architecture, PCB layout, manufacturing, commissioning.
Highlights Driving the load with high current thanks to this board. Successfully built 5 pieces

Typical flow I recommend

  1. Clarify requirements: latency, throughput, clock domains, interfaces, and resource budget.
  2. Define architecture: block diagram, dataflow, buffering, and pipeline stages.
  3. Write RTL: clean, parameterizable modules with clear separation of control/datapath.
  4. Verification: testbenches, corner cases, assertions, and regression runs.
  5. Synthesis & implementation: constraints, timing analysis, and iterations until stable.
  6. On‑board validation: bring‑up, measurements, and comparison to expected behavior.
  7. Documentation: brief design notes and usage information for future maintainers.

Contact

If you are interested in collaboration, feel free to reach out.

Email: mamior12(at)gmail.com
City: Warsaw, Poland